This invention relates to a priority level controlled interrupt handler unit for providing rapid handling of interrupt requests.
Rapid handling of interrupt requires is an important function in electronic data processing systems, particularly in systems for real time process control. For example, in process control systems, interrupt requests from many data sources, associated with sampled process variables, e.g. temperature, pressure, humidity, flow quantities, etc., may require rapid real time analysis potentially leading to changes in process execution.
Similarly, in other data processing applications requiring intermodule communication and control, rapid and adaptive processing of interrupt requests is desirable. For example housekeeping functions of structured programs performed in a multi-programming mode may require rapid and adaptive execution for optimal effectiveness.
Previous solutions for rapid servicing of interrupt requests are based on very expensive devices having complex circuit structures. Although such devices may provide requisite speeds of reaction they are unreliable due to their complicated structures.
For example, German Auslegeschrift No. 1 234 059, discloses a control device applicable to a multi-processing system for allocating priority levels to various computers of the system which mutually assign or re-assign programs or program parts having different priority levels. Each computer receives dynamically only the priority level of the program part it is processing at the moment, as long as it contains said particular program part. The system allocates program levels under control of a shift register structure which assigns priority levels in fixed associations with groups of shift stages. The assignment is conducted by shifting a computer address, or other identification number, in the shift register in the direction associated with increasing or decreasing priority levels, depending on the priority of the program part being executed in the addressed computer.
However, this device does not provide priority-controlled servicing of interrupt requests having differing priority, but merely allocates priority levels to different computers of a multi-processor system.
A priority level controlled interrupt handler device which is particularly applicable to data processing systems offering medium to lower range performance but requiring extremely fast reaction to interrupt requests, is disclosed in U.S. Pat. No. 4,172,284 granted Oct. 23, 1979 to H. J. Heinrich et al. That device includes a shift register having stages permanently and fixedly associated with specific interrupt levels (priority levels). The stages are connected to associated comparison units for comparing interrupt levels indicated in shifted interrupt requests with interrupt levels associated with respective stages. The device also contains a stack which buffers priority sublevel functions also contained in the interrupt requests. For controlling entries into this buffer, circuits are provided for testing the state of the stack (full, not full, empty, etc.). Each stage is also associated with a base address register and an instruction address register, the latter receiving an address formed by adding a function associated with the respective interrupt level to the base address. The address received by the instruction address register indicates the first instruction of an interrupt routine required for the execution or servicing of an interrupt request of a corresponding interrupt source.
Due to the serial transfer of interrupt requests through the shift register and the fixed allocation of interrupt levels to the stages of the shift register, and thus to the control facilitates connected to the outputs of the shift register, the associated request servicing operations are too slow for many applications and not sufficiently adaptable.